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Silicon Labs /BGM210PA32JIA /MODEM_NS /DIRECTMODE

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Interpret as DIRECTMODE

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DMENABLE)DMENABLE 0 (SYNCASYNC)SYNCASYNC 0 (ADD0)SYNCPREAM 0CLKWIDTH

SYNCPREAM=ADD0

Description

No Description

Fields

DMENABLE

Enable Direct Mode
SYNCASYNC

Choose Synchronous or Asynchronous mode
SYNCPREAM

Synchronous mode preamble

0 (ADD0): No preamble bits appended

1 (ADD8): 8 preamble bits appended

2 (ADD16): 16 preamble bits appended

3 (ADD32): 32 preamble bits appended
CLKWIDTH

Synchronous mode clock pulse width

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data